(a) Field of the Invention
The invention relates to a shift register, particularly to a shift register constructed by amorphous silicon thin-film transistors.
(b) Description of the Related Art
Typically, thin-film transistor liquid crystal displays (TFT-LCDs) are divided into two types, the amorphous silicon TFT LCD (a-Si TFT-LCD) and the polycrystalline silicon TFT LCD (poly-Si TFT-LCD). An amorphous silicon thin-film transistor is often used in an active matrix type LCD due to its low fabrication cost and high production yield; however, some of its electrical characteristics are inferior compared with a polycrystalline silicon thin-film transistor. Thus, an amorphous silicon gate (ASG) technology accompanied by many testified circuit architectures is proposed to combine with the application of the amorphous silicon thin-film transistor, so that the amorphous silicon thin-film transistor may compare favorably with the polycrystalline silicon thin-film transistor when they are used in a high-resolution display.
FIG. 1A shows a block diagram illustrating a shift register 10 provided in a conventional gate drive circuit that is constructed by amorphous silicon thin-film transistors. Referring to FIG. 1A, the shift register 10 includes 193 unit stages 111-11193 for respectively driving 192 scan lines, where a unit stages 11193 is a dummy unit stage and not connected with any scan line. Each unit stage includes an input terminal IN′, an output terminal OUT′, a feedback control terminal CT′, a clock signal input terminal CK′, a first power voltage terminal VSS′ and a second power voltage terminal VDD′.
In the shift register 10, an output signal OUTM−1 (M is a positive integer; 1<M≦193) of a preceding unit stage 11M−1 serves as the input signal IN of a succeeding unit stage 11M, and an output signal OUTM of the succeeding unit stage 11M in turn serves as the feedback control signal CT for the preceding unit stage 11M−1. Thus, the unit stages 11 may drive their respective scan lines in succession.
FIG. 1B shows a detailed circuit diagram of one unit stage 11 shown in FIG. 1A. The unit stage 11 includes a pull-up unit 111, a pull-up drive unit 112, a pull-down unit 113, a pull-down drive unit 114, a floating preventing unit 115, and a turn-on preventing unit 116. Note that all the transistors in the unit stage 11 are amorphous silicon thin-film transistors.
The pull-up unit 111 includes an NMOS transistor Q1. The drain of the NMOS transistor Q1 is connected to the clock signal input terminal CK′ for receiving a clock signal CK/CKB, its gate is connected to a first node N1, and its source is connected to the output terminal OUT′ for outputting an output signal OUT. The pull-up drive unit 112 includes a capacitor C and three NMOS transistors Q3, Q4 and Q5. The two ends of the capacitor C are respectively connected to the first node N1 and the output terminal OUT′. The drain and the gate of the transistor Q3 are connected with each other; also, its gate is connected to the input terminal IN′ for receiving the input signal IN, and its source is connected to the first node N1. The drain of the transistor Q4 is connected to the first node N1, its gate is connected to a second node N2, and its source is connected to the first power voltage terminal VSS′ for receiving a first power voltage VSS of a first power voltage source. The first power voltage VSS may have a low voltage level or a ground level. The drain of the transistor Q5 is connected to the first node N1, its gate is connected to the feedback control terminal CT′ for receiving the feedback control signal CT, and its source is connected to the first power voltage terminal VSS′. The pull-down unit 113 includes a NMOS transistor Q2 whose drain is connected to the output terminal OUT′, gate is connected to the second node N2, and source is connected to the first power voltage terminal VSS′. The pull-down drive unit 114 includes two NMOS transistors Q6 and Q7. The drain of the transistor Q6 is connected to the second power voltage terminal VDD′, its gate is connected to the feedback control terminal CT′, and its source is connected to the second node N2. The drain of the transistor Q7 is connected to the second node N2, its gate is connected to the input terminal IN′, and its source is connected to the first power voltage terminal VSS′. The floating preventing unit 115 includes an NMOS transistor Q8 whose drain and gate are connected with each other to form a diode architecture. Further, the drain of the NMOS transistor Q8 is connected to the second power voltage terminal VDD′, and its source is connected to the second node N2. The turn-on preventing unit 116 includes an NMOS transistor Q9 whose drain is connected to the second node N2, gate is connected to the output terminal OUT′, and source is connected to the first power voltage terminal VSS′.
The operations of a conventional shift register are described below with reference to FIGS. 1A and 1B, with a third unit stage 113 being taken as an example.
During operation, the shift register 113 receives an output signal Out2 (input signal IN) of a preceding unit stage 112 via the input terminal IN′ and receives a clock signal CK via the clock signal input terminal CK′ to enable the output signal Out3 of the unit stage 113 to have a high level. Then, the output signal Out3 of the unit stage 113 is disabled to have a low level according to the output signal Out4 (feedback control signal CT) of a succeeding unit stage 114 transmitted via the feedback control terminal CT′. During the scanning process of the shift register 10, each the output signals Out1-Out192 in turn is enabled and then disabled; in other words, once the output signal Out3 of the unit stage 113 is enabled, the unit stage 113 will not proceed the next action until the remaining unit stages 111-112 and unit stage 114-11193 all finish proceeding their respective current actions. Thus, the NMOS transistors Q2 and Q4 in each unit stage 11 must be turned on for a long time to keep the output signal OUT disabled. Further, the positively biased NMOS transistors Q2 and Q4 may become zero-biased only as an input signal having a high level is received and the output signal OUT is enabled. Therefore, since the NMOS transistors Q2 and Q4 are always positively biased for a long time, they are liable to malfunction to result in a considerable shift in the threshold voltage Vth of a transistor.
More specifically, during the long-term operation of the unit stage 11, the threshold voltage Vth2 of the NMOS transistor Q2 is continually increased to cause an increase in the on-resistance between the output terminal OUT′ and the first power voltage terminal VSS′. In that case, a low dynamic response speed of the output signal OUT is achieved when the voltage of the output signal OUT is changed from the second power voltage VDD to the first power voltage VSS, and the output signal OUT often influenced by surrounding signals or noises to thus hardly maintain its voltage at the first power voltage VSS. This may cause the gate drive circuit to transmit distorted scan signals to result in drive errors. Also, the threshold voltage Vth4 of the NMOS transistor Q4 is continually increased to cause an increase in the on-resistance between the first node N1 and the first power voltage terminal VSS′. In that case, a low dynamic response speed at the first node N1 is achieved when the voltage of the first node N1 is changed from the second power voltage VDD to the first power voltage VSS, and the output signal OUT often influenced by surrounding signals or noises to thus hardly maintain its voltage at the first power voltage VSS. For example, when the clock signal CK is in a high level period, it may erroneously turn on the NMOS transistor Q1 to enable the output signal OUT in case the voltage of the first node N1 is deviated from normal one due to the influence of noises. Under the circumstance, the gate drive circuit may transmit distorted scan signals to result in drive errors that worsen the display quality of a display panel.
FIG. 2 shows a block diagram illustrating a unit stage 21 of another conventional shift register. Referring to FIG. 2, the unit stage 21 includes eight amorphous silicon NMOS transistors M1, M2a, M2b, M3, M4, M5, M6 and M7. The pull down unit 211 is divided into a first pull-down transistor M2a and a second pull-down transistor M2b, and the gate of the transistor M2b. Hence, though the second NMOS transistor M2b, similar to the NMOS transistor Q2 or Q4 shown in FIG. 1B, is positively biased for a long time to result in a considerable shift in the threshold voltage, the provision of the first pull-down transistor M2a whose gate is controlled by the output signal OUTi+1 (i is a positive integer) of a succeeding unit stage 21 may cure this problem. More specifically, when the voltage of the output signal OUTi is changed from the second power voltage VDD to the first power voltage VSS, the first NMOS transistor M2a may cooperate with the second NMOS transistor M2b to pull down the voltage of an output node to improve the dynamic response speed.
However, the first NMOS transistor M2a may relieve the shift in the threshold voltage only at the moment the output signal OUTi is pulled down, but, at the remaining moments, the shift in the threshold voltage of the NMOS transistor M2b still influences the operation of the unit stage 21 to result in drive errors.